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ds07-16310-1e fujitsu semiconductor data sheet 32-bit microcontroller cmos fr30 s eries MB91F127/f128 n description this model, designed on the basis of 32-bit risc cpu (fr30 series), is a standard single-chip micro controller with built-in i/o resources and bus control functions. the functions are suitable for built-in control that requires high-speed cpu processing. MB91F127 includes 256 kbytes built-in flash memory and 14 kbytes built-in ram. mb91f128 includes 510 kbytes built-in flash memory and 14 kbytes built-in ram. the specifications of the devices are best suited for applications requiring high-level cpu processing capabilities, such as navigation system, high-performance fax, and printer controller. n features fr-cpu ? 32-bit risc (fr30), load/store architecture, 5-step pipeline ? operating frequency : internal 25 mhz ? general register : 32bit x 16 registers ? 16-bit fixed-length instructions (primitives), 1 instruction/1 cycle ? instructions of memory-to-memory transfer, bit processing, and barrel shift : instructions suitable for built-in control (contin ued) n pac k ag e 100 pin, plastic lqfp (fpt-100p-m05)
MB91F127/f128 2 ? function entry/exit instructions, multi load/store instruction for register data : high-level language compatible instructions ? register interlock functions : simple description of assembler language ? branch instructions with delay slot : reduced overhead on branching process ? built-in multiplier/ supporting at instruction level signed 32-bit multiplying : 5 cycles signed 16-bit multiplying : 3 cycles ? interrupt (saving pc and ps) : 6 cycles, 16 priority levels bus interface ? maximum of 25 mhz internal operation rate ? 25-bit address bus (32 mb space) ? 16-bit address output, 8/16-bit data input/output ? basic bus cycle : 2-clock cycle ? chip selection outputs specifiable in a minimum of 64 kbytes steps : 6 outputs ? automatic wait cycle : specifiable flexibly from 0 cycle to 7 cycles for each area ? supporting time-division input/output interface for address/data (for area 1 only) ? unassigned data/address terminals are available as input/output ports ? supporting little endian mode (selecting one area from area 1 to area 5) dmac (dma controller) ? 8 channels ? transfer factor : interrupt request of built-in resources ? transfer sequence : step transfer/block transfer/burst transfer/consecutive transfer ? transfer data length : selectable among 8 bits, 16 bits, and 32 bits ? pausing is allowed by interrupt request uart ? 3 channels ? full-duplex double buffer ? data length : 7 to 9 bits (no parity), 6 to 8 bits (with parity) ? asynchronous (start-stop synchronization) or clk synchronous communication is selectable ? multi processor mode ? built-in 16-bit timer (u-timer) used as a baud-rate generator : generates an arbitrary baud rate ? external clock is available as a transfer clock ? error detection : parity, frame, and overrun a/d converter (sequential transducer) ? 8/10-bit resolution, 8 channels ? sequential comparison and transducer : at 25 mhz, 5.2 m s ? built-in sample and hold circuit ? conversion mode : selectable among single conversion, scan conversion, and repeat conversion ? activation : selectable among software, external trigger, and built-in timer reload timer ? 16-bit timer : 3 channels ? internal clock : 2-clock cycle resolution, selectable among 2/8/32 dividing and external clock (continued)
MB91F127/f128 3 (continued) other interval timers ? 16-bit timer : 3 channels (u-timer) ? ppg timer : 4 channels ? 16-bit ocu : 4 channels, icu : 4 channels, free-run timer : 1 channel ? watchdog timer: 1 channel flash memory 510 kb ? 510 kb flash rom: read/write/erase is allowed with a same power built- in ram 14 kb ? d-bus ram 12 kb, c-bus ram 2 kb bit search module ? position of a first bit that changes between 1 and 0 is searched in one cycle, within an msb of one word. interrupt controller ? external interrupt input : normal interrupt 6 (int0 to int5) ? internal interrupt factors : uart, dmac, a/d, reload timer, utimer, delay interrupt, ppg, icu, and ocu ? priority levels are programmable (16 levels) reset factors ? power-on reset/watchdog timer/software reset/external reset low power consumption mode ? sleep/stop mode clock control ? built-in pll circuit, selectable among 1-multiplication, and 2-multiplication ? gearing function : operation clock frequencies are freely and independently specifiable for cpu and peripherals. gear clocks are selectable among 1/1, 1/2, 1/4, and 1/8 (or among 1/2, 1/4, 1/8, and 1/16). upper limit of peripheral operations is 25 mhz. others ? package : lqfp-100 ? cmos technology : 0.35 m m ? power supply voltage : 3.3 v 0.3 v n series configuration model name MB91F127 mb91f128 mb91fv129 outline quantity production quantity production evaluation product flash memory 256 kb 510 kb 510 kb d-bus ram 12 kb 12 kb 16 kb c-bus ram 2 kb 2 kb 2 kb
MB91F127/f128 4 n pin assignment 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 pg5/oc1 pg6/oc2 pg7/oc3 vcc pa6/clk pa5/cs5/sc1 pa4/cs4/si1 pa3/cs3/so1 pa2/cs2 pa1/cs1 pa0/cs0 p86/ale hst rst vss md0 md1 md2 p80/rdy p81/bgrnt/in0 p82/brq/in1 p83/rd p84/wr0 p85/wr1 p20/d16 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 pj3/an3 pj2/an2 pj1/an1 pj0/an0 avss/avrl avrh avcc p70/a24/frck/tci2 p67/a23/in3 p66/a22/in2 vss p65/a21 p64/a20 p63/a19 p62/a18 p61/a17 p60/a16 p57/a15 p56/a14 p55/a13 p54/a12 p53/a11 p52/a10 p51/a09 p50/a08 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 pg4/oc0 pg3/ocpa3 pg2/ocpa2 pg1/ocpa1 pg0/ocpa0 pe0/int0 pe1/int1 vcc x0 x1 vss pe2/int2 pe3/int3 pe4/int4/tci1 pe5/int5/sc0 pe6/si0 pe7/so0 pf3/sc2/atg pf2/so2 pf1/si2 pf0/tci0 pj7/an7 pj6/an6 pj5/an5 pj4/an4 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 p21/d17 p22/d18 p23/d19 p24/d20 p25/d21 p26/d22 p27/d23 p30/d24 p31/d25 p32/d26 p33/d27 p34/d28 p35/d29 p36/d30 vss p37/d31 p40/a00 vcc p41/a01 p42/a02 p43/a03 p44/a04 p45/a05 p46/a06 p47/a07 (top view) (fpt-100p-m05)
MB91F127/f128 5 n pin description note that the numbers in the table are not pin numbers on a package. (continued) no. pin name input/output circuit type description 1 2 3 4 5 6 7 8 d16/p20 d17/p21 d18/p22 d19/p23 d20/p24 d21/p25 d22/p26 d23/p27 d bit 16 through bit 23 of external data bus. the terminals are available as general i/o ports (p20 through p27) when external bus width is specified at 8 bits or in single- chip mode. 9 10 11 12 13 14 15 16 d24/p30 d25/p31 d26/p32 d27/p33 d28/p34 d29/p35 d30/p36 d31/p37 d bit 24 through bit 31 of external data bus. the terminals are available as general i/o ports (p30 through p37) when the terminals are not used. 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 a00/p40 a01/p41 a02/p42 a03/p43 a04/p44 a05/p45 a06/p46 a07/p47 a08/p50 a09/p51 a10/p52 a11/p53 a12/p54 a13/p55 a14/p56 a15/p57 d bit 00 through bit 15 of external address bus. the terminals are available as general i/o ports (p40 through p47 and p50 through p57) when the terminals are not used as address buses. 33 34 35 36 37 38 39 40 a16/p60 a17/p61 a18/p62 a19/p63 a20/p64 a21/p65 a22/p66/in2 a23/p67/in3 d bit 16 through bit 23 of external address bus. the terminals are available as general i/o ports (p60 through p67) when the terminals are not used as address busses. [in2,in3]: input terminals of input capture. this function is active when input capture is operating.
MB91F127/f128 6 (continued) no. pin name input/output circuit type description 41 a24/p70/frck/ tci2 d bit 24 of external address bus. [p70] a24, frck and tci2 are available as general input ports when they are not used. [frck] external clock input of free-run timer. this function is active when external clock input of free-run timer is used. [tci2] external clock input of timer 2. this function is active when external clock input of timer 2 is used. 42 rdy/p80 d external ready input. enter 0 when bus cycle under execution does not complete. this terminal is available as general input/ output port when it is not used. 43 bgrnt /p81/in0 d external bus open receive output. this terminal outputs l when an external bus is released. this terminal is available as general input/output port when it is not used. [in0] input capture input. this function is active when input capture is under input opera- tion. 44 brq/p82/in1 d external bus open request input. enter 1 when releasing exter- nal bus. this terminal is available as general input/output port when it is not used. [in1] input capture input. this function is active when input capture is under input opera- tion. 45 rd /p83 d external bus read strobe. this terminal is available as general input/output port when it is not used. 46 wr0 /p84 d external bus write strobe.control signals and data bus byte po- sitions are related as the following : 47 wr1 /p85 d 48 49 50 cs0 /pa0 cs1 /pa1 cs2 /pa2 d chip select 0 output (low active) chip select 1 output (low active) chip select 2 output (low active) [pa0,1,or 2] available as general input/output ports when cs0 , cs1 and cs2 are not used. note : wr1 is set to hi-z during resetting. for using with 16-bit bus width, use an external pull-up resistor. [p84 or p85] available as general input/output ports when wr0 and w r1 are not used. 16-bit bus width 8-bit bus width single chip mode d31 to d24 wr0 wr0 (port allowed) d23 to d16 wr1 (port allowed) (port allowed)
MB91F127/f128 7 (continued) no. pin name input/output circuit type description 51 52 53 cs3 /pa3/so1 cs4 /pa4/si1 c s5 /pa5/sc1 d chip select 3, 4, 5 output (low active). [pa3,4,5] available as general input/output ports when channel 1 of chip select uart is not used. [so1,si1,sc1] data output, data input, and clock terminals of uart1. active when uart1 operation is allowed. 54 clk/pa6 d system clock output. outputs a same clock as the same fre- quency of external bus operation. [pa6] available as general input/output ports it is not used. 55 56 57 58 59 60 61 62 ocpa0/pg0 ocpa1/pg1 ocpa2/pg2 ocpa3/pg3 oc0/pg4 oc1/pg5 oc2/pg6 oc3/pg7 d [ocpa0 to 3] ppg timer outputs. the function is active when ppg timer output is allowed. [oc0 to 3] output comparison output. the function is active when output comparison output is allowed. [pb0-7] available as general input/output ports it is not used. 63 64 65 md0 md1 md2 b mode terminals 0 through 2. the terminals specify basic opera- tion mode of mcu. use the terminals by connecting them directly to vcc or vss. 66 67 x0 x1 a clock (oscillation) input. clock (oscillation) output. 68 rst c external reset input. 69 hst c hardware standby input. 70 p86/ale d [ale] address latch signal output. the function is active when ale output of epcr is allowed. 71 72 int0/pe0 int1/pe1 int2/pe2 int3/pe3 d [int0,1,2,3] external interrupt request inputs. the input is used whenever necessary if external interrupt is allowed. output of other functions must be suspended if not on purpose. [pe0,1,2,3] general input/output port 75 76 int4/pe4/tci1 int5/pe5/sc0 d [int4,5] external interrupt request inputs.the input is used whenever necessary if concerned external interrupt is allowed. output of other functions must be suspended if not on purpose. [tci1] external clock input of timer 1. [sc0] clock input of uart0. [pe4,5] general input/output port 77 si0/pe6 d [si0] data input of uart0.this function is active when data in- put of uart0 is allowed. [pe6]general input/output port 78 so0/pe7 d [so0] data output of uart0.this function is active when data output of uart0 is allowed. [pe7] general input/output port
MB91F127/f128 8 (continued) note : most of the above terminals multiplex inputs and outputs of i/o ports and resources, as indicated as xxxx/ pxx. if the outputs of ports and resources conflict with each other on the terminals, resources take prefer- ences. no. pin name input/output circuit type description 79 pf0/tci0 d [tci0] external clock input of timer 0. [pf0] general input/output port 80 si2/pf1 d [si2] data input of uart2.this function is active when data in- put of uart2 is allowed. [pf1] general input/output port 81 so2/pf2 d [so2] data output of uart2.this function is active when data output of uart2 is allowed. [pf2] general input/output port. this function is active when data output of uart2 is disallowed. 82 sc2/pf3/atg d [sc2] clock input of uart2 [atg ]external trigger input of a/d converter the input is used whenever necessary if a function concerned is selected. output of other functions must be suspended if not on purpose. [pf3] general input/output port 83 to 90 an0/pj0 an1/pj1 an2/pj2 an3/pj3 an4/pj4 an5/pj5 an6/pj6 an7/pj7 e [an0 to an7] analog input of a/d converter. this function is active when analog input is specified in aic reg- ister. [pj0 through pj7] general input/output ports 91 avcc ? vcc power supply for a/d converter 92 avrh ? reference voltage of a/d converter (high potential side). be sure to turn on or off this terminal with a potential higher than avrh applied to vcc. 93 avss/avrl ? a/d converter vss power source and reference voltage (low po- tential side). 94 to 96 vcc ? power sources of digital circuits. be sure to connect power source to all terminals when the device is used. 97 to 100 vss ? ground level of digital circuits.
MB91F127/f128 9 n input/output circuit type type circuit remarks a ? for 25 mhz system ? oscillation feedback register : approx. 1m w ? standby control is available. b ? cmos level input ? high-voltage control is avail- able for flash test. c ? cmos level hysteresis input ? standby control is not avail- able. d ? cmos level output ? cmos level hysteresis input ? standby control is available e ? standby control is available ? cmos level output ? cmos level hysteresis input ? analog input x1 x0 clock input standby diffused resistor control signal mode input p-channel transistor n-channel transistor cmos digital input diffused resistor digital output digital output digital input diffused resistor standby digital output digital output digital input diffused resistor analog input standby
MB91F127/f128 10 n handling devices 1. preventing latch up on a cmos ic, latch up may occur when a voltage higher than vcc or a voltage lower than vss is applied to input terminal or output terminal, or when a voltage exceeding rated level is applied across vcc and vss. latch up causes drastic increase of power source current, which may result in destruction of the element by heat. take extra care not to exceed maximum rating in use. also, take extra care so that analog terminal does not exceed digital power source. 2. treatment of unused input terminals leaving unused terminals open may cause malfunction. apply pull-up or pull-down treatment on unused terminals. 3. external reset input complete resetting of internal system requires inputting l level signal to rst terminal for a minimum of 5 machine cycles. 4. notes on using external clock when using an external clock, supply a clock signal to x0 terminal and supply its antiphase clock to x1 terminal simultaneously. in this case, do not use stop mode (oscillation stop mode). (because x1 terminal halts with "h" output under stop status.) under a 12.5 mhz frequency, the device operates with a clock supplied to x0 terminal only. figures show examples of using an external clock. example of using external clock (normal) note : stop mode (oscillation stop mode) is not available. example of using external clock (allowed under operation at 12.5 mhz or lower frequency) x0 x1 x0 x1 open
MB91F127/f128 11 5. connecting power supply terminals (vcc, vss) if two or more vcc, vss terminals are used, the terminals to be placed under the same potentials are connected with each other internally for preventing malfunctions such as latch up. however, for reducing unwanted radiation, preventing malfunctions of strobe signals and observing total power and current ratings, be sure to connect all of these terminals to power supply and ground externally. connecting power supply to vcc - vss in impedance as low as possible is desirable. 6. crystal oscillator circuit noises around x0 and x1 terminals causes malfunction of the device. design printed wiring so that x0, x1, and crystal oscillator (or ceramic oscillator), and bypass capacitor to the ground are aligned as close as possible one another. also the wiring of those elements should not cross with other wiring if possible. printed wiring with ground wires around x0 and x1 terminals ensures more stable operations. such designing is strongly recommended. 7. treating nc terminals be sure to leave nc terminals open. 8. mode terminals (md0 through md2) do not connect the mode terminals directly to vcc or vss. for preventing malfunctions caused by noises, make printed traces between the mode terminals and vcc or vss as short as possible, and connect the elements in lower impedance. 9. turning power on be sure to turn on the power of the device with rst terminal placed under "l" level. ensure a period at a minimum of 5 cycles of internal operation clock before placing the terminal under "h" level. 10. terminal status upon turning on power status upon turning on the power is indefinite. upon turning on the power, oscillation starts and the circuit is initialized. 11. oscillation input upon turning on power upon turning on the power, be sure to input a clock signal until oscillation stabilizing wait status is released. 12. initializing power-on reset the device includes some built-in registers that are initialized only with power-on reset operation. for initializing the registers, perform power-on reset by turning on the power again. 13. recovery from sleep/stop status for recovering from sleep/stop status initiated by a program in c-bus ram, reset the device instead of recovering by an interrupt process.
MB91F127/f128 12 n block diagram fr cpu ram (12 kbytes) dma controller (8 ch.) bit search module clock control unit (watchdog timer) interrupt control unit uart (3 ch) reload timer (3 ch) ppg icu, ocu free run timer port e, f, g, j 10-bit a/d converter (8 ch.) bus converter (32 bits - 16 bits) bus converter (harvard - princeton) bus controller port2, 3, 4, 5, 6, 7, 8, a ram (2 kbytes) flash memory MB91F127:256 kb mb91f128:510 kb d-bus (32 bits) r-bus (16 bits) c-bus (32 bits) i-bus (16 bits) x0 x1 rst hst int0 to int5 an0 to an7 avcc avss/avrl avrh at g si0 to si2 so0 to so2 sc0 to sc2 tci0 to tci2 oc0 to oc3 in0 to in3 frck ocpa0 to ocpa3 d16 to d31 a00 to a24 rd wr0, wr1 rdy clk brq bgrnt cs0 to cs5 ale 6 8 3 3 3 3 4 4 4 16 25 2 6 notes : terminals are described in functional groups (actual terminals are partially multiplexed). for using realos, perform time management by external interrupt or built-in timer.
MB91F127/f128 13 n cpu core memory space ? MB91F127 0000 0000 h 0000 0400 h 0000 0800 h 0000 1000 h 0000 4000 h 0001 0000 h ffff ffff h 0001 0000 h 0008 0000 h 0008 0800 h 0010 0000 h ffff ffff h i/o i/o i/o i/o i/o i/o flash rom 256 kb flash rom 256 kb 000c 0000 h external rom external bus mode internal rom external bus mode single-chip mode access inhibit internal ram 12 kb access inhibit external area access inhibit internal ram 12 kb access inhibit access inhibit internal ram 12 kb access inhibit external area internal ram 2 kb internal ram 2 kb access inhibit direct addressing areas i/o map external area access inhibit note : external area is not accessible in single-chip mode. when accessing to external areas, select the internal rom external bus mode in mode register. direct addressing areas the areas described below are used for i/o processes. the areas, referred to as direct addressing areas, allow specifying an operand address directly by an instruction. the direct addressing areas varies as the following, depending on size of the data to be accessed. ? byte-data access : 0 to 0ff h ? half-word data access : 0 to 1ff h ? word-data access : 0 to 3ff h access inhibit access inhibit
MB91F127/f128 14 ? mb91f128 0000 0000 h 0000 0400 h 0000 0800 h 0000 1000 h 0000 4000 h 0001 0000 h ffff ffff h 0001 0000 h 0008 0000 h 0008 0800 h 0010 0000 h ffff ffff h i/o i/o i/o i/o i/o i/o flash rom 510 kb flash rom 510 kb external rom external bus mode internal rom external bus mode single-chip mode access inhibit internal ram 12 kb access inhibit external area access inhibit internal ram 12 kb access inhibit access inhibit internal ram 12 kb access inhibit external area internal ram 2 kb internal ram 2 kb access inhibit direct addressing areas i/o map external area access inhibit note : external area is not accessible in single-chip mode. when accessing to external areas, select the internal rom external bus mode in mode register. direct addressing areas the areas described below are used for i/o processes. the areas, referred to as direct addressing areas, allow specifying an operand address directly by an instruction. the direct addressing areas varies as the following, depending on size of the data to be accessed. ? byte-data access : 0 to 0ff h ? half-word data access : 0 to 1ff h ? word-data access : 0 to 3ff h
MB91F127/f128 15 n legend of i/o map note : register bit values indicate initial values as shown below : 1 : initial value1 0 : initial value0 x : initial value x - : register does not exist physically in this position. address register internal resource + 0 + 1 + 2 + 3 000000 h pdr3 [r/w] xxxxxxxx pdr2 [r/w] xxxxxxxx - - - - - - - - - - - - - - - - port data register read/write attribute initial register value after reset register name (the register listed in the first column is at address 4n, the register listed in the second column is at address 4n + 1, - - - ) leftmost register address (the first column register is on the msb side of data in word access mode)
MB91F127/f128 16 n i/o map (continued) address register internal resource + + + + 0 + + + + 1 + + + + 2 + + + + 3 000000 h pdr3 [r/w] xxxxxxxx pdr2 [r/w] xxxxxxxx ?? port data register 000004 h pdr7 [r/w] - - - - - - - x pdr6 [r/w] xxxxxxxx pdr5 [r/w] xxxxxxxx pdr4 [r/w] xxxxxxxx 000008 h ? pdra [r/w] xxxxxxxx ? pdr8[r/w] - - xxxxxx 00000c h ? 000010 h ?? pdre [r/w] xxxxxxxx pdrf [r/w] xxxxxxxx 000014 h pdrg [r/w] xxxxxxxx ?? pdrj [r/w] xxxxxxxx 000018 h ???? reserved 00001c h ssr [r/w] 00001- 00 sidr [r/w] xxxxxxxx scr [r/w] 00000100 smr [r/w] 00 - - 0 - 00 uart0 000020 h ssr [r/w] 00001- 00 sidr [r/w] xxxxxxxx scr [r/w] 00000100 smr [r/w] 00 - - 0 - 00 uart1 000024 h ssr [r/w] 00001- 00 sidr [r/w] xxxxxxxx scr [r/w] 00000100 smr [r/w] 00 - - 0 - 00 uart2 000028 h tmrlr [w] xxxxxxxx xxxxxxxx tmr [w] xxxxxxxx xxxxxxxx reload timer 0 00002c h ? tmcsr [r/w] - - - - 0000 00000000 000030 h tmrlr [w] xxxxxxxx xxxxxxxx tmr [w] xxxxxxxx xxxxxxxx reload timer 1 000034 h ? tmcsr [r/w] - - - - 0000 00000000 000038 h ?? reserved 00003c h tmrlr [w] xxxxxxxx xxxxxxxx tmr [w] xxxxxxxx xxxxxxxx reload timer 2 000040 h ? tmcsr [r/w] - - - - 0000 00000000 000044 h ipcp1[r] xxxxxxxx xxxxxxxx ipcp0[r] xxxxxxxx xxxxxxxx 16 bit icu 000048 h ipcp3[r] xxxxxxxx xxxxxxxx ipcp2[r] xxxxxxxx xxxxxxxx 00004c h ? ics23[r/w] 00000000 ? ics01[r/w] 00000000 000050 h adcr [w] 00101-xx xxxxxxxx adcs [r/w] 000000000 00000000 a/d converter (serially com- pared)
MB91F127/f128 17 (continued) address register internal resource + + + + 0 + + + + 1 + + + + 2 + + + + 3 000054 h occp1[r/w] xxxxxxxx xxxxxxxx occp0[r/w] xxxxxxxx xxxxxxxx 16 bit ocu 000058 h occp3[r/w] xxxxxxxx xxxxxxxx occp2[r/w] xxxxxxxx xxxxxxxx 00005c h ?? reserved 000060 h ?? 000064 h ocs2, 3[r/w] xxx00000 0000xx00 ocs0, 1[r/w] xxx00000 0000xx00 16 bit ocu 000068 h ?? reserved 00006c h tcdt [r/w] 00000000 00000000 tccs [r/w] 0 - - - - - - - 00000000 free run timer 000070 h ?? reserved 000074 h ?? reserved 000078 h utm/utimr [r/w] 00000000 00000000 ? utimc[r/w] 0 - - 00001 u-timer0 00007c h utm/utimr [r/w] 00000000 00000000 ? utimc[r/w] 0 - - 00001 u-timer1 000080 h utm/utimr [r/w] 00000000 00000000 ? utimc[r/w] 0 - - 00001 u-timer2 000084 h ?? reserved 000088 h ?? 00008c h ?? reserved 000090 h ?? 000094 h eirr [r/w] 00000000 enir [r/w] 00000000 ? external interrupt/ nmi 000098 h ehvr [r/w] - - - - 0000 elvr [r/w] 00000000 ?
MB91F127/f128 18 (continued) address register internal resource + + + + 0 + + + + 1 + + + + 2 + + + + 3 00009c h ? reserved 0000a0 h ? 0000a4 h ? 0000a8 h ? 0000ac h ? 0000b0 h ? 0000b4 h ? 0000b8 h ? 0000bc h ? 0000c0 h ? 0000c4 h ? 0000c8 h ? 0000cc h ? 0000d0 h ?? ddre [w] 00000000 ddrf [w] 00000000 port direction register 0000d4 h ? aic3[w] 11111111 ?? a/d converter 0000d8 h ddrg [w] 00000000 ?? ddrj [w] 00000000 port direction reg- ister 0000dc h gcn1 [r/w] 00110010 00010000 - - - - - - - - gcn2[r/w] 00000000 ppg ctl 0000e0 h ptmr0 [r] 11111111 11111111 pcsr0 [w] xxxxxxxx xxxxxxxx ppg0 0000e4 h pdut0 [w] xxxxxxxx xxxxxxxx pcnh0[r/w] 0000000 - pcnl0[r/w] 00000000 0000e8 h ptmr1 [r] 11111111 11111111 pcsr1 [w] xxxxxxxx xxxxxxxx ppg1 0000ec h pdut1 [w] xxxxxxxx xxxxxxxx pcnh1[r/w] 0000000 - pcnl1[r/w] 00000000 0000f0 h ptmr2 [r] 11111111 11111111 pcsr2 [w] xxxxxxxx xxxxxxxx ppg2 0000f4 h pdut2 [w] xxxxxxxx xxxxxxxx pcnh2[r/w] 0000000 - pcnl2[r/w] 00000000 0000f8 h ptmr3 [r] 11111111 11111111 pcsr3 [w] xxxxxxxx xxxxxxxx ppg3 0000fc h pdut3 [w] xxxxxxxx xxxxxxxx pcnh3[r/w] 0000000 - pcnl3[r/w] 00000000
MB91F127/f128 19 (continued) address register internal resource + + + + 0 + + + + 1 + + + + 2 + + + + 3 000100 h to 0001fc h ? reserved 000200 h dpdp [r/w] - - - - - - - - - - - - - - - - - - - - - - - - -0000000 dmac 000204 h dacsr [r/w] 00000000 00000000 00000000 00000000 000208 h datcr [r/w] - - - - - - - - - - xx0000 - - xx0000 - - xx0000 00020c h ? 000210 h to 0002fc h ? reserved 000300 h to 0003ec h ? reserved 0003f0 h bsd0 [w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx bit search module 0003f4 h bsd1 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0003f8 h bsdc [w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0003fc h bsrr [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
MB91F127/f128 20 (continued) address register internal resource + + + + 0 + + + + 1 + + + + 2 + + + + 3 000400 h icr00 [r/w] - - -11111 icr01[r/w] - - -11111 icr02[r/w] - - -11111 icr03[r/w] - - -11111 interrupt controller 000404 h icr04[r/w] - - -11111 icr05[r/w] - - -11111 icr06[r/w] - - -11111 icr07[r/w] - - -11111 000408 h icr08 [r/w] - - -11111 icr09[r/w] - - -11111 icr10[r/w] - - -11111 icr11[r/w] - - -11111 00040c h icr12[r/w] - - -11111 icr13[r/w] - - -11111 icr14[r/w] - - -11111 icr15[r/w] - - -11111 000410 h icr16[r/w] - - -11111 icr17[r/w] - - -11111 icr18[r/w] - - -11111 icr19[r/w] - - -11111 000414 h icr20[r/w] - - -11111 icr21[r/w] - - -11111 icr22[r/w] - - -11111 icr23[r/w] - - -11111 000418 h icr24 [r/w] - - -11111 icr25[r/w] - - -11111 icr26[r/w] - - -11111 icr27[r/w] - - -11111 00041c h icr28[r/w] - - -11111 icr29[r/w] - - -11111 icr30[r/w] - - -11111 icr31[r/w] - - -11111 000420 h icr32[r/w] - - -11111 icr33[r/w] - - -11111 icr34[r/w] - - -11111 icr35[r/w] - - -11111 000424 h icr36[r/w] - - -11111 icr37[r/w] - - -11111 icr38[r/w] - - -11111 icr39[r/w] - - -11111 000428 h icr40[r/w] - - -11111 icr41[r/w] - - -11111 icr42[r/w] - - -11111 icr43[r/w] - - -11111 00042c h icr44[r/w] - - -11111 icr45[r/w] - - -11111 icr46[r/w] - - -11111 icr47[r/w] - - -11111 000430 h dicr [r/w] - - - - - - - 0 hrcl [r/w] - - -11111 ?? delay interrupt 000434 h to 00047c h ? reserved 000480 h rsrr/wtcr [r/w] 1xxxx - 00 stcr [r/w] 000111- - pddr [r/w] - - - - 0000 ctbr [w] xxxxxxxx clock controller block 000484 h gcr [r/w] 110011 - 1 wpr [w] xxxxxxxx ?? 000488 h ptcr [r/w] 00 - - 0 - - - ? pll controller block 00048c h to 0005fc h ? reserved
MB91F127/f128 21 (continued) note : do not issue rmw instructions to a register with write-only bit. data in reserved or - area is indefinite. address register internal resource + + + + 0 + + + + 1 + + + + 2 + + + + 3 000600 h ddr3 [w] 00000000 ddr2 [w] 00000000 ?? data direction reg- ister 000604 h ddr7 [w] - - - - - - - 0 ddr6 [w] 00000000 ddr5 [w] 00000000 ddr4 [w] 00000000 000608 h ? ddra [w] -0000000 ? ddr8 [w] - - 000000 00060c h asr1 [w] 00000000 00000001 amr1 [w] 00000000 00000000 external bus inter- face 000610 h asr2 [w] 00000000 00000010 amr2 [w] 00000000 00000000 000614 h asr3 [w] 00000000 00000011 amr3 [w] 00000000 00000000 000618 h asr4 [w] 00000000 00000100 amr4 [w] 00000000 00000000 00061c h asr5 [w] 00000000 00000101 amr5 [w] 00000000 00000000 000620 h amd0 [r/w] - - - xx111 amd1 [r/w] 0 - - 00000 amd32[r/w] 00000000 amd4 [r/w] 0 - - 00000 000624 h amd5[r/w] 0 - - 00000 dscr [w] 00000000 rfcr [r/w] --xxxxxx 00 - - - 000 000628 h epcr0 [w] - - 1 - 1100 -1111111 epcr1 [w] - - - - - - - 1 11111111 00062c h dmcr4 [r/w] 00000000 0000000- dmcr5 [r/w] 00000000 0000000- 000630 h to 0007bc h ? reserved 0007c0 h fstr [r/w] 000xxxx0 ??? flash memory 0007c4 h to 0007f8 h ? reserved 0007fc h ? ler [w] - - - - - 000 modr [w] xxxxxxxx little endian regis- ter mode register rmw instructions (rmw : read modify write) and rj, @ri or rj, @ri eor rj, @ri andh rj, @ri orh rj, @ri eorh rj, @ri andb rj, @ri orb rj, @ri eorb rj, @ri bandl #u4, @ri borl #u4, @ri beorl #u4, @ri bandh #u4, @ri borh #u4, @ri beorh #u4, @ri
MB91F127/f128 22 n interrupt causes, interrupt vectors and interrupt control register allocations (continued) interrupt causes interrupt number interrupt level tbr default address* 2 decimal hexadecimal register* 1 offset reset 0 00 ? 3fc h 000ffffc h reserved by system 1 01 ? 3f8 h 000ffff8 h reserved by system 2 02 ? 3f4 h 000ffff4 h reserved by system 3 03 ? 3f0 h 000ffff0 h reserved by system 4 04 ? 3ec h 000fffec h reserved by system 5 05 ? 3e8 h 000fffe8 h reserved by system 6 06 ? 3e4 h 000fffe4 h reserved by system 7 07 ? 3e0 h 000fffe0 h reserved by system 8 08 ? 3dc h 000fffdc h reserved by system 9 09 ? 3d8 h 000fffd8 h reserved by system 10 0a ? 3d4 h 000fffd4 h reserved by system 11 0b ? 3d0 h 000fffd0 h reserved by system 12 0c ? 3cc h 000fffcc h reserved by system 13 0d ? 3c8 h 000fffc8 h undefined instruction exception 14 0e ? 3c4 h 000fffc4 h nmi request 15 0f 15 (f h ) fixed 3c0 h 000fffc0 h external interrupt 0 16 10 icr00 3bc h 000fffbc h external interrupt 1 17 11 icr01 3b8 h 000fffb8 h external interrupt 2 18 12 icr02 3b4 h 000fffb4 h external interrupt 3 19 13 icr03 3b0 h 000fffb0 h uart 0 reception complete 20 14 icr04 3ac h 000fffac h uart 1 reception complete 21 15 icr05 3a8 h 000fffa8 h uart 2 reception complete 22 16 icr06 3a4 h 000fffa4 h uart 0 transmission complete 23 17 icr07 3a0 h 000fffa0 h uart 1 transmission complete 24 18 icr08 39c h 000fff9c h uart 2 transmission complete 25 19 icr09 398 h 000fff98 h
MB91F127/f128 23 (continued) interrupt causes interrupt number interrupt level tbr default address* 2 decimal hexadecimal register* 1 offset dmac 0 (end, error) 26 1a icr10 394 h 000fff94 h dmac 1 (end, erro) 27 1b icr11 390 h 000fff90 h dmac 2 (end, erro) 28 1c icr12 38c h 000fff8c h dmac 3 (end, erro) 29 1d icr13 388 h 000fff88 h dmac 4 (end, erro) 30 1e icr14 384 h 000fff84 h dmac 5 (end, erro) 31 1f icr15 380 h 000fff80 h dmac 6 (end, erro) 32 20 icr16 37c h 000fff7c h dmac 7 (end, erro) 33 21 icr17 378 h 000fff78 h a/d (sequential type) 34 22 icr18 374 h 000fff74 h reload timer 0 35 23 icr19 370 h 000fff70 h reload timer 1 36 24 icr20 36c h 000fff6c h reload timer 2 37 25 icr21 368 h 000fff68 h external interrupt 4 38 26 icr22 364 h 000fff64 h external interrupt 5 39 27 icr23 360 h 000fff60 h reserved by system 40 28 icr24 35c h 000fff5c h reserved by system 41 29 icr25 358 h 000fff58 h u-timer 0 42 2a icr26 354 h 000fff54 h u-timer 1 43 2b icr27 350 h 000fff50 h u-timer 2 44 2c icr28 34c h 000fff4c h flash memory 45 2d icr29 348 h 000fff48 h reserved by system 46 2e icr30 344 h 000fff44 h reserved by system 47 2f icr31 340 h 000fff40 h ppg0 48 30 icr32 33c h 000fff3c h ppg1 49 31 icr33 338 h 000fff38 h ppg2 50 32 icr34 334 h 000fff34 h ppg3 51 33 icr35 330 h 000fff30 h icu0 (capture) 52 34 icr36 32c h 000fff2c h icu1 (capture) 53 35 icr37 328 h 000fff28 h icu2 (capture) 54 36 icr38 324 h 000fff24 h icu3 (capture) 55 37 icr39 320 h 000fff20 h
MB91F127/f128 24 (continued) *1 : icr specifies interrupt levels for interrupt requests, using the registers in interrupt controller. icr is provided for each interrupt request. *2 : tbr is a register that indicates a head address of the vector table for eit. an address that is found by adding offset values defined by tbr and eit cause, is a vector address. *3 : if realos/fr is used, 0x40 and 0x41 interrupts are used for system code. information : an 1 kbyte area starting with an address indicated by tbr is the vector area for eit. size of the area for one vector is 4 byte. relation between a vector number and a vector address is as follows: interrupt causes interrupt number interrupt level tbr default address* 2 decimal hexadecimal register* 1 offset ocu0 (match) 56 38 icr40 31c h 000fff1c h ocu1 (match) 57 39 icr41 318 h 000fff18 h ocu2 (match) 58 3a icr42 314 h 000fff14 h ocu3 (match) 59 3b icr43 310 h 000fff10 h reserved by system 60 3c icr44 30c h 000fff0c h 16 bit free-run timer 61 3d icr45 308 h 000fff08 h reserved by system 62 3e icr46 304 h 000fff04 h delay interrupt cause bit 63 3f icr47 300 h 000fff00 h reserved by system (used by realos) *3 64 40 ? 2fc h 000ffefc h reserved by system (used by realos) *3 65 41 ? 2f8 h 000ffef8 h used by int 66 to 255 42 to ff ? 2f4 h to 000 h 000ffef4 h to 000ffc00 h vctadr = tbr + vctofs = tbr + ( 3fc h - 4 vct) vctadr vector address, vctofs: vector offset, vct: vector number
MB91F127/f128 25 n electrical characteristics 1. absolute maximum ratings (v ss = av ss = 0 v) *1 : care must be taken that av cc , avrh do not exceed v cc + 0.3 v. also, care must be taken that avrh do not exceed av cc . *2 : maximum output current defines a peak value of a specific terminal. *3 : average output current defines a mean value of current flow within a period of 100 ms in a specific terminal. *4 : average total output current defines a mean value of current flow within a period of 100 ms in all terminals. *5 : aplicable to pins : d16 to d31, a00 to a24, rdy, bgrnt , brq, rd , wr0 , wr1 , cs0 to cs5 , clk, ocpa0 to ocpa3, oc0 to oc3, ale, int0 to int5, si0, si2, so0, so2, tci0, sc2 use within recommended operating conditions. use at dc voltage (current) . the + b signal should always be applied with a limiting resistance placed between the + b signal and the microcontroller. (continued) parameter symbol rating unit remarks min max power supply voltage v cc v ss - 0.3 v ss + 4.0 v analog supply voltage av cc v ss - 0.3 v ss + 4.0 v *1 analog reference voltage avrh v ss - 0.3 v ss + 4.0 v *1 input voltage v i v ss - 0.3 v cc + 0.3 v analog input voltage v ia v ss - 0.3 a vcc + 0.3 v output voltage v o v ss - 0.3 v cc + 0.3 v maximum clamp current i clamp - 2.0 + 2.0 ma *5 total maximum clamp current s | i clamp | ? 20 ma *5 l level maximum output current i ol ? 10 ma *2 l level average output current i olav ? 4ma*3 l level maximum total output cur- rent s i ol ? 100 ma l level average total output cur- rent s i olav ? 50 ma *4 h level maximum output current i oh ?- 10 ma *2 h level average output current i ohav ?- 4ma*3 h level maximum total output cur- rent s i oh ?- 50 ma h level average total output cur- rent s i ohav ?- 20 ma *4 power consumption pd ? 500 mw operating temperature t a - 30 + 70 c storage temperature tstg - 55 + 150 c
MB91F127/f128 26 (continued) the value of the limiting resistance should be set so that when the signal is applied the input current to the microcontroller pins does not exceed rated values, either instantaneously or for prolonged periods. note that when the microcontroller drive current is low, such as in the power saving modes, the + b input potential may pass through the protective diode and increase the potential at the vcc pin, and this may affect other devices. note that if a + b signal is input when the microcontroller power supply is off (not fixed at 0 v) , the power supply is provided from the pins, so that incomplete operation may result. note that if the + b input is applied during power-on, the power suplly is provided from the pins and the resulting supply voltage may not be sufficient to operate the power-on reset. care must be taken not to leave the input pin open. sample recommended circuits warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. ? input/output equivalent circuits p-ch n-ch v cc r + b input (0 v to 16 v) limiting resistance protective diode
MB91F127/f128 27 2. recommended operating conditions (v ss = av ss = 0 v) warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol value unit remarks min max power supply v cc 3.0 3.6 v normal operation 2.0 3.6 retain ram data under stop condition analog supply voltage av cc v ss - 0.3 v ss + 3.6 v analog reference voltage avrh av ss av cc v operating temperature t a - 30 + 70 c
MB91F127/f128 28 3. dc characteristics (av cc = v cc = 3.3 v 0.3 v, av ss = v ss = 0 v, t a = - 30 c to + 70 c) * : refer to n input/output circuit type. parameter symbol pin name condition value unit remarks min typ max h level input voltage v ihs hysteresis input terminal ? 0.8 v cc ? v cc + 0.3 v * l level input voltage v ils hysteresis input terminal ? v ss - 0.3 ? 0.2 v cc v* h level output voltage v oh port2 to portj v cc = 3.3 v i oh = - 4.0 ma v cc - 0.5 ?? v l level output voltage v ol port2 to portj v cc = 3.3 v i ol = 4.0 ma ?? 0.4 v input leak current i li port2 to portj v cc = 3.6 v v ss < vi < v cc ?? 5 m a power supply current i cc vcc 25 mhz v cc = 3.3 v ? 75 100 ma i cc 25 mhz v cc = 3.3 v ? 85 120 ma flash writing i ccs 25 mhz v cc = 3.3 v ? 60 85 ma sleeping i cch t a = 25 c v cc = 3.3 v ? 10 150 m astopping input capacity c in other than avcc, avss, avrh, vcc, vss ?? 10 ? pf
MB91F127/f128 29 4. ac characteristics (1) clock timing ratings (v cc = 3.3 v 0.3 v, av ss = v ss = 0 v, t a = - 30 c to + 70 c) *1 : although pll allows selection among x1 and x2 multiplication modes, the selection is limited by oscillation frequency as follows: specifying "x2 multiplication" is not allowed if oscillation frequency exceeds 12.5 mhz. *2 : frequency regulation indicates a maximum fluctuation from a specified center frequency under locked frequency multiplication. parameter symbol condition value unit remarks min max clock frequency (high speed, automatic oscil- lation) f c ? 10 25 mhz self oscillation allowable range clock frequency (high speed, pll used) 10 25 mhz pll-use allowable area for self oscillation and external clock input *1 clock frequency (high speed, 1/2 division in- put) 10 25 mhz external clock input allowable range clock cycle time t c 40 100 ns frequency regulation (when locked) d f ? 10 % *2 input clock pulse width p wh , p wl ? 9.5 ? ns input clock rise and fall time t cr t cf ?? 8ns (t cr + t cf ) internal operation clock frequency cpu system f cp ? 0.625 * 3 25 mhz peripheral system f cpp 0.625 * 3 25 mhz internal operation clock cycle time cpu system t cp 40 1600 * 3 ns peripheral system t lcpp 40 1600 * 3 ns +a a f o f o -a d f = 100 (%)
MB91F127/f128 30 *3 : this is a value in the case where 10 mhz signal, a minimum value of clock frequency, is input to x0 and where 1/2-division in oscillation circuit and 1/8-gear are used. 0.8 v cc 0.2 v cc tcf tcr t c p wh p wl 3.6 3.0 25 frequency (mhz) source voltage (v) operation-guaranteed area (t a = - 30 c to + 70 c)
MB91F127/f128 31 (2) clock output timing (v cc = 3.3 v 0.3 v, av ss = v ss = 0 v, t a = - 30 c to + 70 c) *1 : t cyc is a frequency of 1 clock cycle indicating gear cycle. *2 : the values indicate specifications where x1 gear cycle is used. if gear cycle of 1/2, 1/4, or 1/8 is specified, calculate in the formula below by substituting 1/2, 1/4, or 1/8 into n. min : (1 - n / 2) t cyc - 10 max : (1 - n / 2) t cyc + 10 *3 : the values indicate specifications where x1 gear cycle is used. if gear cycle of 1/2, 1/4, or 1/8 is specified, calculate in the formula below by substituting 1/2, 1/4, or 1/8 into n. min : n / 2 t cyc - 10 max : n / 2 t cyc + 10 clock output timing (3) reset input ratings (v cc = 3.3 v 0.3 v, av ss = v ss = 0 v, t a = - 30 c to + 70 c) parameter symbol pin name condition value unit remarks min max cycle time t cyc clk ? t cp ? ns *1 clk - ? clk t chcl clk 1 / 2 t cyc - 10 1 / 2 t cyc + 10 ns *2 clk ? clk - t clch clk 1 / 2 t cyc - 10 1 / 2 t cyc + 10 ns *3 parameter symbol pin name condition value unit remarks min max reset input time t rstl rst ? t cp 5 ? ns clk v oh v ol v oh t cyc tc lch t chcl rst 0.2 v cc t rstl
MB91F127/f128 32 (4) power-on reset (v cc = 3.3 v 0.3 v, v ss = 0 v, t a = - 30 c to + 70 c) parameter symbol pin name condition value unit remarks min max power supply rise time t r vcc v cc = 3.3 v ? 20 ms v cc < 0.2 v before turning on power power supply shut off time t off vcc ? 2 ? ms oscillation stabiliz- ing wait time t osc ?? 2 t c 2 21 + 100 m s ? ns 0.2 v t r 0.9 v cc vcc vss 2.0 v 3.3 v vcc rst vcc t off t osc t rstl a sudden change of supply voltage may activate the power-on reset function. it is recommended that power voltage should be changed smoothly with less fluctuation of voltages. retaining ram data the rising slope is recommended to be less than 50 mv / ms. be sure to turn on the power while keeping rst terminal at l level first. when the power becomes v cc level, rise the voltage to h level after a period of t rstl .
MB91F127/f128 33 (5) normal bus access read/write operation (v cc = 3.3 v 0.3 v, v ss = 0 v, t a = - 30 c to + 70 c) *1 : if the bus is expanded by automatic wait insertion or rdy input, add time (tcyc the number of expanded cycles) to the rated value. *2 : the ratings are based on conditions with gear cycle 1. if gear cycle of 1/2, 1/4, or 1/8 is specified, calculate in the formula below by substituting 1/2, 1/4, or 1/8 into n. formula : (2 - n / 2) t cyc - 25 parameter symbol pin name condition value unit remarks min max cs0 to cs5 delay time t chcsl clk cs0 to cs5 ? ? 15 ns cs0 to cs5 delay time t chcsh ? 15 ns address delay time t chav clk a24 to a00 ? 15 ns data delay time t chdv clk d31 to d16 ? 15 ns rd delay time t clrl clk rd ? 15 ns rd delay time t clrh ? 15 ns wr0 , 1 delay time t clwl clk wr0 , 1 ? 15 ns wr0 , 1 delay time t clwh ? 15 ns valid address ? valid data input time t avdv a24 to a00 d31 to d16 ? 3 / 2 tcyc - 25 ns *1 *2 rd ? valid data input time t rldv rd d31 to d16 ? tcyc - 25 ns *1 data setup ? rd - time t dsrh 25 ? ns rd -? data hold time t rhdx 0 ? ns
MB91F127/f128 34 t cyc t chcsh t chcsl t chav t clrl t clrh t rldv t avdv t rhdx 2.4 v 2.4 v 2.4 v 0.8 v 0.8 v 2.4 v t dsrh clk cs0 ~ cs5 a24 ~ a00 rd d31 ~ d16 0.8 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 2.4 v read 2.4 v 0.8 v 0.8 v write data 2.4 v clk wr a24 ~ a00 0.8 v 2.4 v 0.8 v 2.4 v d31 ~ d16 0.8 v 2.4 v 0.8 v 2.4 v t clwh t clwl t chdv (wr0 ~ wr1)
MB91F127/f128 35 (6) timeshared bus access read/write operations (v cc = 3.3 v 0.3 v, v ss = 0 v, t a = - 30 c to + 70 c) * : if the bus is expanded by automatic wait insertion or rdy input, add time (tcyc x the number of expanded cycles) to the rated value. parameter symbol pin name condition value unit remarks min max ale delay time t cllh2 clk ale ? ? 10 ? ale delay time t clll2 ? 10 ? cs1 delay time t chcsl2 clk cs1 ? 15 ? cs1 delay time t chcsh2 ? 15 ns address delay time t chav2 clk d31 to d16 ? 15 ns data delay time t chdv2 ? 15 ns rd delay time t clrl2 clk rd ? 10 ns rd delay time t clrh2 ? 10 ns wr0 , 1 delay time t clwl2 clk wr0 wr1 ? 10 ns wr0 , 1 pulse width t clwh2 ? 10 ns rd ? valid data input time t rldv2 rd d31 to d16 ? t cyc - 25 ? * data setup ? rd - time t dsrh2 25 ? ns rd -? data hold time t rhdx2 0 ? ns
MB91F127/f128 36 t cyc t cllh2 t chcsl2 t chav2 t chcsh2 t rldv2 ma1 ma1 ba1 ba1 t rhdx2 t clrh2 t clrl2 t chdv2 t clwl2 t clwh2 t chav2 t chav2 t dsrh2 t clll2 2.4 v 0.8 v 2.4 v 2.4 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 0.8 v 0.8 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 2.4 v 0.8 v 2.4 v 0.8 v 0.8 v 2.4 v clk ale cs1 rd wr0 - wr1 d31-d16 multiplex bus for reading d31-d16 multiplex bus for writing a15-a08 for non-multi address read address write
MB91F127/f128 37 (7) ready input timing (v cc = 3.3 v 0.3 v, av ss = v ss = 0 v, t a = - 30 c to + 70 c) parameter symbol pin name condition value unit remarks min max rdy setup time rclk t rdys rdy clk ? 15 ? ns clk ? rdy hold time t rdyh clk rdy 0 ? ns clk rdy rdy 2.4 v 0.8 v 2.4 v 2.4 v 0.8 v 0.8 v 2.4 v 0.8 v t rdyh t rdys t rdyh t rdys t cyc with waiting without waiting
MB91F127/f128 38 (8) hold timing (v cc = 3.0 v 0.3 v, av ss = v ss = 0 v, t a = - 30 c to + 70 c) note : more than one cycle is required for bgrnt to change after brq is input. parameter symbol pin name condition value unit remarks min max bgrnt delay time t chbgl clk bgrnt ? ? 10 ns bgrnt delay time t chbgh ? 10 ns terminal floating ? bgrnt time t xhal bgrnt t cyc - 10 t cyc + 10 ns bgrnt - ? terminal valid time t hahv t cyc - 10 t cyc + 10 ns 0.8 v 2.4 v t chbgl t xhal t hahv t chbgh t cyc brq bgrnt clk 2.4 v 2.4 v 2.4 v 2.4 v each pin high-z
MB91F127/f128 39 (9) uart timing (v cc = 3.3 v 0.3 v, v ss = 0 v, t a = - 30 c to + 70 c) * : t cycp is a cycle time of peripheral system clock. internal shift clock mode external shift clock mode parameter symbol pin name condition value unit remarks min max serial clock cycle time t scyc ? internal shift clock mode 8 t cycp * ? ns sc ? so delay time t slov ?- 10 + 50 ns valid si ? sc - t ivsh ? 50 ? ns sc - ? valid si hold time t shix ? 50 ? ns serial clock h pulse width t shsl ? external shift clock mode 4 t cycp * - 10 ? ns serial clock l pulse width t slsh ? 4 t cycp * - 10 ? ns sc ? so delay time t slov ? 050ns valid si ? sc - t ivsh ? 50 ? ns sc - ? valid si hold time t shix ? 50 ? ns serial busy time t busy ?? 6 t cycp *ns cs ? sc, so delay time t clzo ?? 50 ns cs ? sc input mask time t clsl ?? 3 t cycp *ns sc - ? sc, so hi-z time t choz ?? 50 ? ns sc so si t shix t ivsh t slov t scyc sc so si cs t choz t busy t clsl t ivsh t shix t slov t slsh t clzo t shsl
MB91F127/f128 40 (10) trigger input timing (v cc = 3.3 v 0.3 v, v ss = 0 v, t a = - 30 c to + 70 c) * : t cycp is a cycle time of peripheral system clock. parameter symbol pin name condition value unit remarks min max input pulse width t trgh t trgl atg , int0, 1, 2, 3 int4, 5 ? 5 t cycp * ? ns atg int0, 1, 2, 3 int4, 5 t trgh t trgl
MB91F127/f128 41 (11) a/d converter block electrical characteristics (v cc = 3.3 v 0.3 v, av ss = v ss = 0 v, t a = - 30 c to + 70 c) notes : relatively, the errors increase as |avrh| value becomes smaller. define an output impedance of external circuit analog input under the following conditions : output impedance of external circuit 2 (k w ) if an output impedance of external circuit is exceedingly high, sampling time for analog voltage may run short. parameter symbol pin name value unit remarks min typ max resolution ?? ? 10 10 bit total error ?? ? ? 4.0 lsb linearity error ?? ? ? 3.5 lsb differential linearity error ?? ? ? 2.0 lsb zero transition voltage v 0t an0 to an7 avss - 1.5 lsb avss + 0.5 lsb avss + 2.5 lsb mv full-scale transition voltage v fst an0 to an7 avrh - 5.5 lsb avrh - 1.5 lsb avrh + 0.5 lsb mv conversion time ?? 5.3 ??m s analog input current i ain an0 to an7 ? 0.1 10 m a analog input voltage v ain an0 to an7 av ss ? avrh v reference voltage ? avrh av ss ? av cc v power supply current i a avcc ? 3.0 5.0 ma i ah ?? 5.0 m a reference voltage supply current i r avrh ? 100 150 m a i rh ?? 10 m a variation among channels ? an0 to an7 ?? 4lsb
MB91F127/f128 42 analog input circuit model diagram analog input avrh avss/ avrl rin approx. 3.6 k w be switched on, only while a/d conversion is performed. cin = approx 30 pf comparator comparator comparator note : use the values shows as guides only.
MB91F127/f128 43 5. a/d converter block electrical characteristics resolution analog variations recognized by an a/d converter. linearity error deviation of actual conversion characteristics from an ideal line, which is across zero-transition point (00 0000 0000 ?? 00 0000 0001) and full-scale transition point (11 1111 1110 ?? 11 1111 1111) differential linearity error deviation from ideal value of input voltage, which is required for changing output code by 1 lsb. total error difference between actual value and ideal value. the error includes zero-transition error, full-scale transition error, and linearity error. (continued) 3ff 3fe 3fd 004 003 002 001 av ss avrh 0.5 lsb' {1 lsb' ( n - 1 ) + 0.5 lsb'} 1.5 lsb' total error actual characteristics (actual mea- sured value) actual characteristics ideal characteristics analog input digital output total error of digital output n = v nt - {1 lsb (n - 1) + 0.5 lsb} 1 lsb 1 lsb (ideal value) = avrh - av ss 1024 [v] v ot (ideal value) = v nt : transition voltage for digital output to change from (n+1) to n. av ss + 0.5 lsb [v] v fst (ideal value) = avrh - 1.5 lsb [v] v nt
MB91F127/f128 44 (continued) 3ff 3fe 3fd 004 003 002 001 av ss avrh {1 lsb' ( n - 1 ) + v ot } n + 1 n n - 1 n - 2 av ss avrh linearity error of digital output n = v nt - {1 lsb (n - 1) + v ot } 1 lsb [lsb] differential linearity error of digital output n = v ( n + 1 ) t - v nt } 1 lsb - 1 1 lsb = v fst - v ot 1022 [v] v ot : transition voltage for digital output to change from (000) h to (001) h . v fst : transition voltage for digital output to change from (3fe) h to (3ff) h . [lsb] linearity error differential linearity error digital output digital output actual conversion characteristics v fst (actual measured value) v nt (actual measured value) actual conversion characteristics ideal characteristics v ot (actual measured value) analog input analog input ideal characteristics actual conversion characteristics actual conversion characteristics (actual mea- sured value) v nt (actual measured value) v fst
MB91F127/f128 45 n flash memory write/erase characteristics parameter condition value unit remarks min typ max sector erase time t a = + 25 c, v cc = 3.3 v ? 115s not including time for internal writing before deletion. chip erase time ? 4 ? s not including time for internal writing before deletion. half byte (16 bit width) writing time ? 16 3600 m s not including system-level over- head time. write/erase cycle ?? 10,000 ? cycle data holding time ?? 100,000 ? h
MB91F127/f128 46 n example characteristics ? power supply current 60 50 40 30 20 10 0 2.7 3 3.3 3.6 3.9 v cc (v) i ccs (ma) fc = 25 mhz 100 90 70 50 30 10 -10 2.7 3 3.3 3.6 3.9 v cc (v) i cch ( m a) 80 60 40 20 0 fc = 25 mhz 80 70 60 50 40 30 20 10 0 2.7 3 3.3 3.6 3.9 v cc (v) i cc (ma) fc = 25 mhz 10 9 7 5 3 1 -1 2.7 3 3.3 3.6 3.9 v cc (v) i a (ma) 8 6 4 2 0 fc = 25 mhz 180 160 140 100 60 20 2.7 3 3.3 3.6 3.9 v cc (v) i r ( m a) 120 80 40 0 fc = 25 mhz a/d reference power supply current vs. power supply voltage power supply current (stopping) vs. power supply voltage a/d power supply current vs. power supply voltage power supply current (sleeping) vs. power supply voltage power supply current vs. power supply voltage
MB91F127/f128 47 ? output voltage 4 3.6 3.2 2.8 2.4 2 2.7 3 3.3 3.6 3.9 v cc (v) v oh (v) 3.8 3.4 3 2.6 2.2 300 240 180 150 2.7 3 3.3 3.6 3.9 v cc (v) v ol (mv) 270 210 100 10 2.7 3 3.3 3.6 3.9 v cc (v) r (k w ) h output voltage vs. power supply voltage pull-up resistance vs. power supply voltage l output voltage vs. power supply voltage
MB91F127/f128 48 n ordering information part number package remarks MB91F127pfv 100 - pin plastic lqfp (fpt-100p-m05) mb91f128pfv 100 - pin plastic lqfp (fpt-100p-m05)
MB91F127/f128 49 n package dimensions 100-pin plastic lqfp (fpt-100p-m05) *pins width and pins thickness include plating thickness. dimensions in mm (inches) c 2000 fujitsu limited f100007s-3c-5 14.00?.10(.551?004)sq 16.00?.20(.630?008)sq 125 26 51 76 50 75 100 0.50(.020) 0.20?.05 (.008?002) m 0.08(.003) 0.145?.055 (.0057?0022) 0.08(.003) "a" index .059 ?004 +.008 ?.10 +0.20 1.50 (mounting height) 0?8 0.50?.20 (.020?008) 0.60?.15 (.024?006) 0.25(.010) 0.10?.10 (.004?004) details of "a" part (stand off)
MB91F127/f128 fujitsu limited all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. f 0201 ? fujitsu limited printed in japan

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